- 资讯公开站google_news_tsmc
台积电2030年High-NA EUV押注的关键不在机器，而在掩膜
TSMC's 2030 High-NA EUV Bet Isn't About the Machine — It's About the Mask - finance.biggo.com
- 资讯公开站google_news_asml
High-NA EUV 迎来新就绪里程碑：首款高量产逻辑产品
High NA EUV reaches new readiness milestone with first high-volume Logic product - ASML
- 资讯公开站google_news_asml
台积电与ASML宣布合作推动High-NA EUV大尺寸光掩模行业转型
TSMC and ASML Announce Initiative to Pioneer Industry Transition to Large-Format Photomasks for High NA EUV - ASML
- 资讯公开站google_news_asml
英特尔代工与ASML合作加速High-NA EUV的行业准备
Intel Foundry and ASML Collaborate to Accelerate Industry Readiness for High-NA EUV - ASML
- 资讯公开站google_news_tsmc
ASML与TSMC宣布率先推动行业向High-NA EUV大尺寸光掩模过渡
ASML and TSMC Announce Initiative to Pioneer Industry Transition to Large-Format Photomasks for High NA EUV - pr.tsmc.com
- 资讯公开站EE Times
英特尔将High-NA EUV投入量产，但拼接技术仍待验证
Intel Puts High-NA EUV into Production, but Stitching Still Has Something to Prove
摘要显示，Intel已在Panther Lake芯片制造中验证High-NA EUV光刻技术，并投入量产。但报道指出，电气拼接（electrical stitching）和更大掩模版仍是后续需要克服的障碍。
意义：High-NA EUV量产落地将影响先进制程演进，拼接与掩模技术是后续良率与扩展关键。
- 资讯公开站Semiconductor Engineering
在测试晶圆之前预测硅行为
Predicting Silicon Behavior Years Before Test Wafers
摘要显示，该文章讨论用于高数值孔径（high-NA）EUV应用的光学仿真方法，并强调其已通过晶圆验证。文章标题称可在测试晶圆之前数年预测硅行为，但摘要未提供具体技术细节、数据或机构表态。
意义：高NA EUV是下一代光刻关键，提前预测硅行为可缩短开发周期、降低试错成本，对芯片设计与制造开发者有参考价值。
